L2 Cache

Would more help instability?

I’m still not satisfied with the performance of N on my machine; but then, I’m using a 2Ghz Celeron with probably not much L2 cache. I was thinking maybe more L2 cache would help the situation; am I right?

I could afford a full blown P4 but I would like to find one with 1G of cache. I need a sweet deal; anyone know where to get one cheap?

It would probably help, but not nearly as much as you will want. You would get much more out of a faster/more robust processor than worrying about a CPU’s on board cache. Any more modern processor will most likly have L2 on the chip any way. L2 cache is just the icing on the cake really.

HOwever, you should get at least reasonable perfromance from a Celeron 2.0 ghz. Is your CPU maxing out? If so, has freezing tracks helped at all?

I think you may be confusing L2 cache with conventional memory. Cache (L1 & L2) is nowadays built into the processor and would be a couple of Mb rather than Gb. 1Gb of memory could certainly have n-track running more smoothly, as could a faster processor with more cache or faster disks even. You can use utilities such as Sandra to find out where the bottlenecks in your system are.

No, I was thinking cache, maybe I was thinking 1Meg of cache.

I do use freezing, but I don’t want to freeze until I know that what I’m freezing is what I want. So, when I start adding plugins, I get that annoying interrupt, machine gun sound. My cpu runs best at about 10%, but when I get the interrupt, it starts jumping up.

I figured that more onbaord cache would help the program run smoother; isn’t the cache where all the math processing takes place? Educate me! :laugh:

Quote (jsmyers24151 @ April 11 2006,12:15)
I figured that more onbaord cache would help the program run smoother; isn’t the cache where all the math processing takes place? Educate me! :laugh:

Um, no. It is simply memory the processor uses as a temporary holding pen between the RAM and the processor itself. Cache is usually static RAM versus dynamic RAM which is faster but more expensive. (Thus static RAM is not used for the main RAM on a system.)

The math processing takes place in the processor. Or are you thinking of 20 years ago on the 386s where you would add a math coprocessor? The math coprocessor was incorporated into the main CPU starting with the 486.

For effects, you want simple CPU horsepower… more instructions executed per second. Ceratinly RAM is a factor in over all performance, but you can have all the RAM in the world and if your processor is slow, well, it won’t do you any good to reach your goal which is more effects.

From Wikipedia:

<!–QuoteBegin>
Quote
The second issue is the fundamental tradeoff between cache latency and hit rate. Larger caches are both slower and have better hit rates. To ameliorate this tradeoff, many computers use multiple levels of cache, with small fast caches backed up by larger slower caches. As the latency difference between main memory and the fastest cache has become larger, some processors have begun to utilize as many as three levels of on-chip cache. For example, in 2003, Itanium II began shipping with a 6MB unified level 3 cache on-chip. The IBM Power 4 series has a 256MB level 3 cache off chip, shared among several processors.

Multi-level caches generally operate by checking the smallest Level 1 cache first; if it hits, the processor proceeds at high speed. If the smaller cache misses, the next larger cache is checked, and so on, before main memory is checked.

Multi-level caches introduce new design decisions. For instance, in some processors (like the Intel Pentium 2, 3, and 4, as well as most RISCs), the data in the L1 cache may also be in the L2 cache. These caches are called inclusive. Other processors (like the AMD Athlon) have exclusive caches — data is guaranteed to be in at most one of the L1 and L2 caches.

The advantage of exclusive caches is that they store more data. This advantage is larger with larger caches. When the L1 misses and the L2 hits on an access, the hitting cache line in the L2 is exchanged with a line in the L1. This exchange is quite a bit more work than just copying a line from L2 to L1, which is what an inclusive cache does.


Wikipedia is the second place you should look after Google to answer just about any question you might have. :)

Link to the full CPU cache article here.

It would be interesting to know what the system spec’s are on the computer he’s writing this program on. He may be closing in on a mega game status. If he’s writing it on the latest and greatest hardware, I may never catch up to it. This thing certainly has the bells and whistles.